1. Field of the Invention
The present invention relates to the manufacture of metal gate field effect transistors, and more particularly, to metal gate CMOS processing techniques.
2. Description of the Related Art
Conventional processes for fabricating metal gate field effect transistors include the following sequential steps: forming source and drain ("S/D") regions by implanting and/or diffusing dopant ions having the appropriate conductivity type; growing a gate oxide; and forming a metal conductor over the gate oxide. The source and drain regions are spaced apart to define a channel therebetween, and the portion of the gate oxide and the metal conductor overlying the channel are referred as the "gate". The metal portion of the gate must be deposited after the S/D regions have been diffused because the metal (usually aluminum) would not survive the high temperature processing necessary to diffuse the S/D regions. On the other hand, silicon gate FETs can be readily fabricated with self-aligned S/D regions. This is possible because the silicon gate, which unlike aluminum can withstand the high temperature of a diffusion cycle, may be formed before the S/D regions are implanted and diffused.
The acronym "MOS", which stands for metal-oxide-silicon, generally refers to all field effect transistor structures ("FETs"), including those fabricated with metal or polysilicon gates. However, as used herein, "MOS", "metal gate field effect transistor", "metal gate CMOS FET", and similar terms refer only to FETs in which the gates include a metal (aluminum) conductive layer, as opposed to gates which include a polysilicon or a refractory metal (e.g., molydenum or tungsten) conductive layer.
Ideally, a gate (whether metal or polysilicon gate) should overlie the entire channel length with minimal, if any, overlap of the S/D regions. This orientation reduces capacitances associated with the overlap region(s). Such capacitances are known as "parasitic" capacitances. However, in conventional metal gate processes a substantial overlap of the metal gate and both S/D regions is necessary to insure that the metal gate overlies the entire channel. This overlap magnifies the parasitic capacitance of the FET, reducing the switching speed of the FET; ultimately the frequency response of the FET and any circuit including the FET is reduced by the parasitic capacitances.
Optimal gate alignment depends in large part on the nature of the gate material and fabrication process of the gate. For example, in silicon gate technology, a polysilicon gate is deposited on a thin gate oxide layer before the S/D regions are formed. The gate then serves as a mask during the formation of the S/D regions and defines the channel length. As a direct result of this technique, alignment of the gate with the S/D regions is achieved without problems of the mask alignment during processing. The self-alignment technique would be beneficial when fabricating metal gate FETS.
If a conventional self-alignment technique is used to fabricate a metal gate FET, the metal gate would be in place before the regions to be self-aligned with the gate (the S/D regions) are implanted. To fabricate an operational device, the gate material must maintain its integrity throughout subsequent processing steps in the fabrication of the transistor. Aluminum will not tolerate process temperatures associated with the diffusion of the S/D regions and the growth of the gate oxide.
The dopant ions implanted using the gate as a mask must subsequently be activated (or diffused) at an elevated temperature to form S/D regions. The annealing process utilized for this purpose is typically performed at temperatures of 900.degree. C. or greater. Metal gate materials, such as aluminum, will melt and/or evaporate when exposed to these temperatures. For example, an aluminum/silicon eutectic is 577.degree. C., and therefore an aluminum gate will disintegrate at typical annealing and diffusion/drive-in temperatures.